hi

i got this warning msg while synthesizing a verilog design with dc

module "abz" could not be elaborated as it has the template attribute. it has been saved as a template instead.

what does this warning msg mean and how is it to be corrected (if its a problem, which it does look like!)

where can i find a comprehensive information about the various warning , comments etc that dc gives out??
thanks!

Hi every EDA tool indexed list of errors and warning with explanations. DC also has such a list. You should find a pdf in the help menu which leads to various other help pdfs. find the appropriate pdf and use search function to find out your issue.
Hope this helps...