Here I would like to mention 2 different ways to design a counter. Second one is the normal one and the First one is the convenient way. This technique would be useful for some other logics as well.
counter1| Code: |
module counter1(clk1,rst_n1,en1,count1);
input clk1;
input rst_n1;
input en1;
output [2:0] count1;
reg [2:0] count1;
always @ (posedge clk1 or negedge rst_n1)
begin
if (!rst_n1)
count1 <= 3b0;
else
count1 <= count1 + en1;
end
endmodule
|
counter2
| Code: |
module counter2(clk2,rst_n2,en2,count2);
input clk2;
input rst_n2;
input en2;
output [2:0] count2;
reg [2:0] count2;
always @ (posedge clk2 or negedge rst_n2)
begin
if (!rst_n2)
count2 <= 3b0;
else
if (en2)
count2 <= count2 + 1;
else
count2 <= count2;
end
endmodule
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