I'm designing a viterbi decoder and synchronization is very important to my design. Is there a way I could put a constraint on a process(clk) not to run except when a certain input say code is known( 1 0r zero)?
i'm thinking of something like

if (clk'event and clk = '1' and code /= "xx")

or this one

if(clk'event and clk = '1' and not(is_x(code)))

but it seems like these statements are not synthesizeable.

Pls help me with ideas.
Thanks
Kazeem

Hi,
u can use clock-enable signal to control ur process. e.g:

process(clkEn,clk)
begin
if (clkEn ='1') then
if (clk'event and clk='1')then
..
..
statements
end if;
end if;
end process;