what is the difference between detecting clk edge using rising_edge/faling_edge function and (event'clk and clk='1')?

There is a small difference between them. please see the snippet from the library std_logic_1164

Code:

FUNCTION rising_edge  (SIGNAL s : std_ulogic) RETURN BOOLEAN IS BEGIN     RETURN (s'EVENT AND (To_X01(s) = '1') AND                          (To_X01(s'LAST_VALUE) = '0')); END; FUNCTION falling_edge (SIGNAL s : std_ulogic) RETURN BOOLEAN IS BEGIN     RETURN (s'EVENT AND (To_X01(s) = '0') AND                          (To_X01(s'LAST_VALUE) = '1')); END;

this function checks the rising or falling edge of the clock as well as the previous value of the clock. but when you write (clk'event and clk='1') you check only the rising or falling edge not the previous value of the signal.

clk'event and clk=1

Here my openion about ur question

clk'event : represents every clock events (i.e) at every cycle

clk=1 : do the function when clk =1, its represent the rising edge.

I ave attached an image file u can refer.

openions about my answer... always welcome

You are absolutely right.

But there is a little advantage using the rising_edge and falling_edge functions.

It is not necessary for the clock that it should to '1' from '0'. It might can also go to '1' from 'X' or 'Z'. In that case the clock is not stabled. Stable clock should swing between '0' and '1'. Just imagine a scenario, you have bug on clock line so the clock looks like this 1,x,1,x,1,x. "clk'event and clk=1" implementaion would consider this as a clock. But rising_edge function will not.

Hope this helps

And one thing you have mentioned that you attached some image but i dont see that. Can you attach it again?