Hi friends will you please help me
module top (Tte, Clk, resetn, out);
input Tte;
input Clk;
input resetn;
output [35:0] out;
…………….
…………….
endmodule
The above module generates the output for 36 bit LFSR. Now I have to give this output of lfsr as input to the c432 bench mark circuit which has a top level module like this
module TopLevel432b (E, A, B, C, PA, PB, PC, Chan);
input[8:0] E, A, B, C;
output PA, PB, PC;
output[3:0] Chan;
wire[8:0] X1, X2, I;
PriorityA M1(E, A, PA, X1);
PriorityB M2(E, X1, B, PB, X2);
PriorityC M3(E, X1, X2, C, PC);
EncodeChan M4(E, A, B, C, PA, PB, PC, I);
DecodeChan M5(I, Chan);
endmodule /* TopLevel432b */

HI FRIENDS NOW WILL YOU PLEASE HELP ME ABOUT HOW TO COMBINE THESE TWO MODULES

Hi,

You should have another top level verilog module which in this will not have any inputs or outputs (unless you have a test bench on top of it). So the two modules will go into this new module as instances. Within the new module, you can have wires connecting both the modules. I am deliberately not giving you the code, you should think of it as hardware, what you have created are two components and to connect these two components you will need wires and the entire unit has to sit on something (which is the new module).

Shabeer
www.vidhyarthe.com