hi all,
i am having problems with some section of mine codes.
use ieee.std_logic_1164.all;

SIGNAL counter : bit_vector(23 DOWNTO 0)

PROCESS (clk20)
BEGIN
IF (clk20'EVENT AND clk20 = '1') THEN
counter<=counter + "000000000000000000000001";
END IF;
END PROCESS;
the complier output this
ERROR: Either Type mismatch or no visible function for this case in C:Actelprjfincomhdl two.vhd line 74.
that's the line with the counter assignment.

it doesn't seem to recognize the 'event function.
i am using libero IDE. thanks

hi,
you cannot do arithmetic operation with bit_vector/std_logic_vector types . So you need to convert that into unsigned, do the arithmetic operation and convert back to bit_vector/std_logic_vector.

your code
counter<=counter + "000000000000000000000001";

my code
counter<=bit_vector(unsigned(counter)+ 1);

this should work...

+Chola

No the code can work with std_logic also just try this

use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;--This lib is must.

SIGNAL counter : std_logic_vector(23 DOWNTO 0)

process(clk20)
begin
if(clk20'event and clk20 = '1')then
counter<=counter + 1;
end if;
end process;

--The imp is its UNSIGNED library. Also always try to use STD LOGIC as it can have 7 values.
Try it all the Best

I have gone thro ur code the problem is with bit and bit_vector change it to std_logic and std_logic_vector, remove library numeric, remove all convergence functions, declare all undeclared variables and compile it will work.
Using STD_LOGIC we get more benefits than BIT. I have tried your code working(only compilation not gone to synthesis).
-Akshay.