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synthesis error in VHDL code (1 viewing)
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TOPIC: synthesis error in VHDL code

#635
priyanka87 (User)
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synthesis error in VHDL code 2012/04/21 01:32 Karma: 0  
Hi...

i have written VHDL code and am facing problem in synthesis in XILINX and giving following error::


ERRORst:787 line 98: Index value <9> is not in Range of array <output_stream>.

can anybody help to solve this problem???
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