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VHDL Glossary

IEEE Std 1076-2002 - IEEE Standard VHDL Language Reference Manual, Copyright © 2006 by the IEEE. The IEEE disclaims any responsibility or liability resulting from the placement and use in this product. Information is reprinted with the permission of the IEEE. Further distribution is not permitted without consent of the IEEE Standards Department. If there is any  questions please  contact admin.


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There are 265 entries in the glossary.
Pages: «1 2 3 4 5 6 7 8 9 »
Term Definition
Belong

(A) (to a range): A property of a value with respect to some range. The value V is said to belong to a range if the relations (lower bound <= V) and (V <= upper bound) are both true, where lower bound and upper bound are the lower and upper bounds, respectively, of the range.

(B) (to a subtype): A property of a value with respect to some subtype. A value is said to belong to a subtype of a given type if it belongs to the type and satisfies the applicable constraint.

 
Binding
The process of associating a design entity and, optionally, an architecture with an instance of a component. A binding can be specified in an explicit or a default binding indication.
 
Bit string literal
A literal formed by a sequence of extended digits enclosed between two quotation (") characters and preceded by a base specifier. The type of a bit string literal is determined from the context.
 
Block
a) The representation of a portion of the hierarchy of a design. A block is either an external block or an internal block.

b) The act of suspending the execution of a process for the purposes of guaranteeing exclusive access to either a file object or an object of a protected type.
 
Bound
A label that is identified in the instantiation list of a configuration specification.
 
Box
The symbol in an index subtype definition, which stands for an undefined range. Different objects of the type need not have the same bounds and direction.
 
Buffer
One possible port mode. A port of mode buffer contributes its driving value to the network containing the port; the design entity containing the port is also allowed to read its driving value.
 
Bus
One kind of guarded signal. A bus floats to a user-specified value when all of its drivers are turned off.
 
ChangeThe signal S, of type T, is said to change value if and only if the expression “S = S’Delayed” evaluates to False, where the "=" operator in the expression is the predefined "=" on type T.
 
Character literalA literal of the character type. Character literals are formed by enclosing one of the graphic characters (including the space and nonbreaking space characters) between two apostrophe (') characters.
 
Character typeAn enumeration type with at least one of its enumeration literals as a character literal.
 
Chosen implementationAn implementation of floating-point types that conforms to either IEEE Std 754-1985 or to IEEE Std 854-1987 and with a minimum representation size of 64 bits.
 
Closely related typesTwo type marks that denote the same type or two numeric types. Two array types are closely related if they have the same dimensionality, if their index types at each position are closely related, and if the array types have the same element types. Explicit type conversion is only allowed between closely related types.
 
CompleteA loop that has finished executing. Similarly, an iteration scheme of a loop is complete when the condition of a while iteration scheme is FALSE or all of the values of the discrete range of a for iteration scheme have been assigned to the iteration parameter.
 
Complete contextA declaration, a specification, or a statement; complete contexts are used in overload resolution.
 
Composite typeA type whose values have elements. There are two classes of composite types: array types and record types.
 
Concurrent statementA statement that executes asynchronously, with no defined relative order. Concurrent statements are used for dataflow and structural descriptions.
 
ConfigurationA construct that defines how component instances in a given block are bound to design entities in order to describe how design entities are put together to form a complete design.
 
ConformTwo subprogram specifications, are said to conform if, apart from certain allowed minor variations, both specifications are formed by the same sequence of lexical elements, and corresponding lexical elements are given the same meaning by the visibility rules. Conformance is defined similarly for deferred constant declarations.
 
ConnectedA formal port associated with an actual port or signal. A formal port associated with the reserved word open is said to be unconnected.
 
ConstantAn object whose value cannot be changed. Constants are either explicitly declared, subelements of explicitly declared constants, or interface constants. Constants declared in packages can also be deferred constants.
 
ConstraintA subset of the values of a type. The set of possible values for an object of a given type that can be subjected to a condition is called a constraint. A value is said to satisfy the constraint if it satisfies the corresponding condition. There are index constraints and range constraints.
 
Conversion functionA function used to convert values flowing through associations. For interface objects of mode in, conversion functions are allowed only on actuals. For interface objects of mode out or buffer, conversion functions are allowed only on formals. For interface objects of mode inout or linkage, conversion functions are allowed on both formals and actuals. Conversion functions have a single parameter. A conversion function associated with an actual accepts the type of the actual and returns the type of the formal. A conversion function associated with a formal accepts the type of the formal and returns the type of the actual.
 
ConvertibleA property of an operand with respect to some type. An operand is convertible to some type if there exists an implicit conversion to that type.
 
Current valueThe value component of the single transaction of a driver whose time component is not greater than the current simulation time.
 
Cycle pureAn expression is cycle pure if its value does not change when evaluated, repeatedly, within a given analog solution point with identical values for all its quantities.
 
Decimal literalAn abstract literal that is expressed in decimal notation. The base of the literal is implicitly 10. The literal may optionally contain an exponent or a decimal point and fractional part.
 
DeclarationA construct that defines a declared entity and associates an identifier (or some other notation) with it. This association is in effect within a region of text that is called the scope of the declaration. Within the scope of a declaration, there are places where it is possible to use the identifier to refer to the associated declared entity; at such places, the identifier is said to be the simple name of the named entity. The simple name is said to denote the associated named entity.
 
Declarative partA syntactic component of certain declarations or statements (such as entity declarations, architecture bodies, and block statements). The declarative part defines the lexical area (usually introduced by a reserved word such as is and terminated with another reserved word such as begin) within which declarations may occur.
 
Declarative regionA semantic component of certain declarations or statements. Certain declarative regions include disjoint parts; for example, the declarative region of a package declaration, which, if there is an associated pacakge body, extends to the end of that package body.
 


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