Enter into Zilicon Zone


RocketTheme Joomla Templates


Read more...
VHDL Glossary

IEEE Std 1076-2002 - IEEE Standard VHDL Language Reference Manual, Copyright © 2006 by the IEEE. The IEEE disclaims any responsibility or liability resulting from the placement and use in this product. Information is reprinted with the permission of the IEEE. Further distribution is not permitted without consent of the IEEE Standards Department. If there is any  questions please  contact admin.


A
You can always search for entries.

Begins withContainsExactly matches

Submit Term/definitions/company

All | A | B | C | D | E | F | G | H | I | K | L | M | N | O | P | Q | R | S | T | U | V | W


There are 265 entries in the glossary.
Pages: «1 2 3 4 5 6 7 8 9 »
Term Definition
DecorateTo associate a user-defined attribute with a named entity and to define the value of that attribute.
 
Default expressionA default value that is used for a formal generic, port, or parameter if the interface object is unassociated. A default expression is also used to provide an initial value for signals and their drivers.
 
Deferred constantA constant that is declared without an assignment symbol (:=) and expression in a package declaration. A corresponding full declaration of the constant must exist in the package body to define the value of the constant.
 
Delta cycleA simulation cycle in which the simulation time at the beginning of the cycle is the same as at the end of the cycle. That is, simulation time is not advanced in a delta cycle. Only nonpostponed processes can be executed during a delta cycle.
 
DenoteA property of the identifier given in a declaration. Where the declaration is visible, the identifier given in the declaration is said to denote the named entity declared in the declaration.
 
Depend

(A) (on a library unit): A design unit that explicitly or implicitly mentions other library units in a use clause. These dependencies affect the allowed order of analysis of design units.

(B) (on a signal value): A property of an implicit signal with respect to some other signal. The current value of an implicit signal R is said to depend on the current value of another signal S if R denotes an implicit signal S'Stable(T), S'Quiet(T), or S'Transaction, or if R denotes an implicit GUARD signal and S is any other implicit signal named within the guard expression that defines the current value of R.

 
Descending rangeA range L downto R.
 
Design entityAn entity declaration together with an associated architecture body. Different design entities may share the same entity declaration, thus describing different components with the same interface or different views of the same component.
 
Design fileOne or more design units in sequence.
 
Design hierarchyThe complete representation of a design that results from the successive decomposition of a design entity into subcomponents and binding of those components to other design entities that may be decomposed in a similar manner.
 
Design libraryA host-dependent storage facility for intermediate-form representations of analyzed design units.
 
Design unitA construct that can be independently analyzed and stored in a design library. A design unit is either an entity declaration, an architecture body, a configuration declaration, a package declaration, or a package body declaration.
 
DesignateA property of access values that relates the value to some object when the access value is nonnull. A nonnull access value is said to designate an object.
 
Designated subtypeFor an access type, the subtype defined by the subtype indication of the access type definition.
 
Designated typeFor an access type, the base type of the subtype defined by the subtype indication of the access type definition.
 
Designator

(A) Syntax that forms part of an association element. A formal designator specifies which formal parameter, port, or generic (or which subelement or slice of a parameter, port, or generic) is to be associated with an actual by the given association element. An actual designator specifies which actual expression, signal, or variable is to be associated with a formal (or subelement or subelements of a formal).An actual designator may also specify that the formal in the given association element is to be left unassociated (with an actual designator of open).

(B) An identifier, character literal, or operator symbol that defines an alias for some other name.

(C) A simple name that denotes a predefined or user-defined attribute in an attribute name, or a user-defined attribute in an attribute specification.

(D) A simple name, character literal, or operator symbol, and possibly a signature, that denotes a named entity in the entity name list of an attribute specification.

(E) An identifier or operator symbol that defines the name of a subprogram.

 
Directly visible
A visible declaration that is not visible by selection. A declaration is directly visible within its immediate scope, excluding any places where the declaration is hidden. A declaration occurring immediately within the visible part of a package can be made directly visible by means of a use clause.
 
Discrete arrayA one-dimensional array whose elements are of a discrete type.
 
Discrete rangeA range whose bounds are of a discrete type.
 
Discrete type
An enumeration type or an integer type. Each value of a discrete type has a position number that is an integer value. Indexing and iteration rules use values of discrete types.
 
DriverA container for a projected output waveform of a signal. The value of the signal is a function of the current values of its drivers. Each process that assigns to a given signal implicitly contains a driver for that signal. A signal assignment statement affects only the associated driver(s).
 
Driving valueThe value a signal provides as a source of other signals.
 
Effective valueThe value obtained by evaluating a reference to the signal within an expression.
 
ElaborationThe process by which a declaration achieves its effect. Prior to the completion of its elaboration (including before the elaboration), a declaration is not yet elaborated.
 
ElementA constituent of a composite type.
 
Entity declaration
A definition of the interface between a given design entity and the environment in which it is used. It may also specify declarations and statements that are part of the design entity. A given entity declaration may be shared by many design entities, each of which has a different architecture. Thus, an entity declaration can potentially represent a class of design entities, each with the same interface.
 
Enumeration literalA literal of an enumeration type. An enumeration literal is either an identifier or a character literal.
 
Enumeration typeA type whose values are defined by listing (enumerating) them. The values of the type are represented by enumeration literals.
 
ErroneousAn error condition that cannot always be detected.
 
ErrorA condition that makes the source description illegal. If an error is detected at the time of analysis of a design unit, it prevents the creation of a library unit for the given design unit. A run-time error causes simulation to terminate.
 


All | A | B | C | D | E | F | G | H | I | K | L | M | N | O | P | Q | R | S | T | U | V | W


Glossary & Definitions
VLSI-world.com