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VHDL Glossary

IEEE Std 1076-2002 - IEEE Standard VHDL Language Reference Manual, Copyright © 2006 by the IEEE. The IEEE disclaims any responsibility or liability resulting from the placement and use in this product. Information is reprinted with the permission of the IEEE. Further distribution is not permitted without consent of the IEEE Standards Department. If there is any  questions please  contact admin.


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There are 265 entries in the glossary.
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Term Definition
SubaggregateAn aggregate appearing as the expression in an element association within another, multidimensional array aggregate. The subaggregate is an (n–1)-dimensional array aggregate, where n is the dimensionality of the outer aggregate. Aggregates of multidimensional arrays are expressed in row-major (right-most index varies fastest) order.
 
SubelementAn element of another element. Where other subelements are excluded, the term element is used.
 
Subprogram specificationSpecifies the designator of the subprogram, any formal parameters of the subprogram, and the result type for a function subprogram.
 
SubtypeA type together with a constraint. A value belongs to a subtype of a given type if it belongs to the type and satisfies the constraint; the given type is called the base type of the subtype. A type is a subtype of itself. Such a subtype is said to be unconstrained because it corresponds to a condition that imposes no restriction.
 
SuspendA process that stops executing and waits for an event or for a time period to elapse.
 
Target libraryA library containing the design unit in which a given component is declared. The target library is used to determine the visible entity declaration under certain circumstances for a default binding indication.
 
Timeout intervalThe maximum time a process will be suspended, as specified by the timeout period in the until clause of a wait statement.
 
TransactionA pair consisting of a value and a time. The value represents a (current or) future value of the driver; the time represents the relative delay before the value becomes the current value.
 
Transport delayAn optional delay model for signal assignment. Transport delay is characteristic of hardware devices (such as transmission lines) that exhibit nearly infinite frequency response: any pulse is transmitted, no matter how short its duration.
 
TypeA set of values and a set of operations.
 
Type conversionAn expression that converts the value of a subexpression from one type to the designated type of the type conversion. Associations in the form of a type conversion are also allowed. These associations have functions and restrictions similar to conversion functions but can be used in places where conversion functions cannot. In both cases (expressions and associations), the converted type must be closely related to the designated type.
 
UnaffectedA waveform in a concurrent signal assignment statement that does not affect the driver of the target.
 
Unassociated formalA formal that is not associated with an actual.
 
Unconstrained subtypeA subtype that corresponds to a condition that imposes no restriction.
 
Unit nameA name defined by a unit declaration (either the primary unit declaration or a secondary unit declaration) in a physical type declaration.
 
Universal_integerAn anonymous predefined integer type that is used for all integer literals. The position number of an integer value is the corresponding value of the type universal_integer.
 
Universal_realAn anonymous predefined type that is used for literals of floating point types. Other floating point types have no literals. However, for each floating point type there exists an implicit conversion that converts a value of type universal_real into the corresponding value (if any) of the floating point type.
 
UpdateAn action on the value of a signal, variable, or file. The value of a signal is said to be updated when the signal appears as the target (or a component of the target) of a signal assignment statement (indirectly); when it is associated with an interface object of mode out, buffer, inout, or linkage; or when one of its subelements (individually or as part of a slice) is updated. The value of a signal is also said to be updated when it is a subelement or slice of a resolved signal, and the resolved signal is updated. The value of a variable is said to be updated when the variable appears as the target (or a component of the target) of a variable assignment statement (indirectly), when it is associated with an interface object of mode out or linkage, or when one of its subelements (individually or as part of a slice) is updated. The value of a file is said to be updated when a WRITE operation is performed on the file object.
 
Upper boundFor a range L to R or L downto R, the larger of L and R.
 
VariableAn object with a single current value.
 
VisibleWhen the declaration of an identifier defines a possible meaning of an occurrence of the identifier used in the declaration. A visible declaration is visible by selection (for example, by using an expanded name) or directly visible (for example, by using a simple name).
 
Visible entity declarationThe entity declaration selected for default binding in the absence of explicit binding information for a given component instance.
 
WaveformA series of transactions, each of which represents a future value of the driver of a signal. The transactions in a waveform are ordered with respect to time, so that one transaction appears before another if the first represents a value that will occur sooner than the value represented by the other.
 
Whitespace characterA space, a nonbreaking space, or a horizontal tabulation character (SP, NBSP, or HT).
 
Working libraryA design library into which the library unit resulting from the analysis of a design unit is placed.
 


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