VHDL Glossary | |
IEEE Std
1076-2002 - IEEE Standard VHDL Language Reference Manual, Copyright © 2006 by the
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| There are 265 entries in the glossary. | |
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| Term | Definition |
| Immediate scope | A property of a declaration with respect to the declarative region within which the declaration immediately occurs. The immediate scope of the declaration extends from the beginning of the declaration to the end of the declarative region. |
| Immediately within | A property of a declaration with respect to some declarative region. A declaration is said to occur immediately within a declarative region if this region is the innermost region that encloses the declaration, not counting the declarative region (if any) associated with the declaration itself. |
| Implicit signal | Any signal S\'Stable(T), S\'Quiet(T), S\'Delayed, or S\'Transaction, or any implicit GUARD signal. A slice or subelement (or slice thereof) of an implicit signal is also an implicit signal. |
| Implicitly declared object | An object whose declaration is not explicit in the source description, but is a consequence of other constructs; for example, signal GUARD. |
| Imply | A property of a binding indication in a configuration specification with respect to the design entity indicated by the binding specification. The binding indication is said to imply the design entity; the design entity is indicated directly, indirectly, or by default. |
| Impure function | A function that may return a different value each time it is called, even when different calls have the same actual parameter values. A pure function returns the same value each time it is called using the same values as actual parameters. An impure function can update objects outside of its scope and can access a broader class of values than a pure function. |
| In | One possible mode of a port or subprogram parameter; also, the only allowed mode of a generic constant. A port of mode in may be read within the design entity containing the port but does not contribute a driving value to the network containing the port. A subprogram parameter of mode in may be read but not modified by the containing subprogram. |
| Incomplete type declaration | A type declaration that is used to define mutually dependent and recursive access types. |
| Incremental binding | A binding indication in a configuration declaration that either reassociates a previously associated local generic or that associates a previously unassociated local port is said to incrementally rebind the component instance or instances to which the binding indication applies. |
| Index constraint | A constraint that determines the index range for every index of an array type, and thereby the bounds of the array. An index constraint is compatible with an array type if and only if the constraint defined by each discrete range in the index constraint is compatible with the corresponding index subtype in the array type. An array value satisfies an index constraint if the array value and the index constraint have the same index range at each index position. |
| Index range | A multidimensional array has a distinct element for each possible sequence of index values that can be formed by selecting one value for each index (in the given order). The possible values for a given index are all the values that belong to the corresponding range. This range of values is called the index range. |
| Index subtype | For a given index position of an array, the index subtype is denoted by the type mark of the corresponding index subtype definition. |
| Inertial delay | A delay model used for switching circuits; a pulse whose duration is shorter than the switching time of the circuit will not be transmitted. Inertial delay is the default delay mode for signal assignment statements. |
| Initial value expression | An expression that specifies the initial value to be assigned to a variable. |
| Inout | One possible mode of a port or subprogram parameter. A port of mode inout may be read within the design entity containing the port and also contributes a driving value to the network containing the port. A subprogram parameter of mode inout may be both read and modified by the containing subprogram. |
| Inputs | The signals identified by the longest static prefix of each signal name appearing as a primary in each expression (other than time expressions) within a concurrent signal assignment statement. |
| Instance | A subcomponent of a design entity whose prototype is a component declaration, design entity, or configuration declaration. Each instance of a component may have different actuals associated with its local ports and generics. A component instantiation statement whose instantiated unit denotes a component creates an instance of the corresponding component. A component instantiation statement whose instantiated unit denotes either a design entity or a configuration declaration creates an instance of the denoted design entity. |
| Integer literal | An abstract literal of the type universal_integer that does not contain a base point. |
| Integer type | A discrete scalar type whose values represent integer numbers within a specified range. |
| Interface list | A list that declares the interface objects required by a subprogram, component, design entity, or block statement. |
| Internal block | A nested block in a design unit, as defined by a block statement. |
| ISO | The International Organization for Standardization. |
| ISO 8859-1 | The ISO Latin-1 character set. Package Standard contains the definition of type Character, which represents the ISO Latin-1 character set. |
| Kernel process | A conceptual representation of the agent that coordinates the activity of user-defined processes during a simulation. The kernel process causes the execution of I/O operations, the propagation of signal values, and the updating of values of implicit signals [such as S\'Stable(T)]; in addition, it detects events that occur and causes the appropriate processes to execute in response to those events. |
| Left of | When both a value V1 and a value V2 belong to a range and either the range is an ascending range and V2 is the successor of V1, or the range is a descending range and V2 is the predecessor of V1. |
| Left-to-right order | When each value in a list of values is to the left of the next value in the list within that range, except for the last value in the list. |
| Library unit | The representation in a design library of an analyzed design unit. |
| Linkage | One possible port mode. A design entity whose entity interface contains a port of mode linkage implies that the behavior of the design entity is not expressed in terms of VHDL semantics. |
| Literal | A value that is directly specified in the description of a design. A literal can be a bit string literal, enumeration literal, numeric literal, string literal, or the literal null. |
| Local generic | An interface object declared in a component declaration that serves to connect a formal generic in the interface list of an entity and an actual generic or value in the design unit instantiating that entity. |
| Glossary & Definitions | |