VHDL Glossary | |
IEEE Std
1076-2002 - IEEE Standard VHDL Language Reference Manual, Copyright © 2006 by the
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| There are 265 entries in the glossary. | |
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| Term | Definition |
| Local port | A signal declared in the interface list of a component declaration that serves to connect a formal port in the interface list of an entity and an actual port or signal in the design unit instantiating that entity. |
| Locally static expression | An expression that can be evaluated during the analysis of the design unit in which it appears. |
| Locally static name | A name in which every expression is locally static (if every discrete range that appears as part of the name denotes a locally static range or subtype and if no prefix within the name is either an object or value of an access type or a function call). |
| Locally static primary | One of a certain group of primaries that includes literals, certain constants, and certain attributes. |
| Locally static subtype | A subtype whose bounds and direction can be determined during the analysis of the design unit in which it appears. |
| Longest static prefix | The name of a signal or a variable name, if the name is a static signal or variable name. Otherwise, the longest static prefix is the longest prefix of the name that is a static signal or variable name. |
| Loop parameter | A constant, implicitly declared by the for clause of a loop statement, used to count the number of iterations of a loop. |
| Lower bound | For a range L to R or L downto R, the smaller of L and R. |
| Match | A property of a signature with respect to the parameter and subtype profile of a subprogram or enumeration literal. The signature is said to match the parameter and result type profile if certain conditions are true. |
| Matching elements | Corresponding elements of two composite type values that are used for certain logical and relational operations. |
| Member | A slice of an object, a subelement, or an object; or a slice of a subelement of an object. |
| Method | An abstract operation that operates atomically and exclusively on a single object of a protected type. |
| Mode | The direction of information flow through the port or parameter. Modes are in, out, inout, buffer, or linkage. |
| Model | The result of the elaboration of a design hierarchy. The model can be executed in order to simulate the design it represents. |
| Name | A property of an identifier with respect to some named entity. Each form of declaration associates an identifier with a named entity. In certain places within the scope of a declaration, it is valid to use the identifier to refer to the associated named entity; these places are defined by the visibility rules. At such places, the identifier is said to be the name of the named entity. |
| Named association | An association element in which the formal designator appears explicitly. |
| Named entity | An item associated with an identifier, character literal, or operator symbol as the result of an explicit or implicit declaration. |
| Net | A collection of drivers, signals (including ports and implicit signals), conversion functions, and resolution functions that connect different processes. Initialization of a net occurs after elaboration, and a net is updated during each simulation cycle. |
| Nonobject alias | An alias whose designator denotes some named entity other than an object. |
| Nonpostponed process | An explicit or implicit process whose source statement does not contain the reserved word postponed. When a nonpostponed process is resumed, it executes in the current simulation cycle. Thus, nonpostponed processes have access to the current values of signals, whether or not those values are stable at the current model time. |
| Null array | Any of the discrete ranges in the index constraint of an array that define a null range. |
| Null range | A range that specifies an empty subset of values. A range L to R is a null range if L > R, and range L downto R is a null range if L |
| Null slice | A slice whose discrete range is a null range. |
| Null transaction | A transaction produced by evaluating a null waveform element. |
| Null waveform element | A waveform element that is used to turn off a driver of a guarded signal. |
| Numeric literal | An abstract literal, or a literal of a physical type. |
| Numeric type | An integer type, a floating point type, or a physical type. |
| Object | A named entity that has a value of a given type. An object can be a constant, signal, variable, or file. |
| Object alias | An alias whose alias designator denotes an object (that is, a constant, signal, variable, or file). |
| Out | One possible mode of a port or subprogram parameter. A port of mode out contributes a driving value to the network containing the port but cannot be read by the design entity containing the port. A subprogram parameter of mode out can be modified but not read by the containing subprogram. |
| Glossary & Definitions | |