VHDL Glossary | |
IEEE Std
1076-2002 - IEEE Standard VHDL Language Reference Manual, Copyright © 2006 by the
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| There are 13 entries in the glossary. | |
| Pages: 1 | |
| Term | Definition |
| Base specifier |
A lexical element that indicates whether a bit string literal is to be interpreted as a binary, octal, or hexadecimal value.
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| Base type |
The type from which a subtype defines a subset of possible values, otherwise known as a constraint. This subset is not required to be proper. The base type of a type is the type itself. The base type of a subtype is found by recursively examining the type mark in the subtype indication defining the subtype. If the type mark denotes a type, that type is the base type of the subtype; otherwise, the type mark is a subtype, and this procedure is repeated on that subtype.
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| Based literal |
An abstract literal expressed in a form that specifies the base explicitly. The base is restricted to the range 2 to 16.
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| Basic operation |
An operation that is inherent in one of the following:
— An assignment (in an assignment statement or initialization) — An allocator — A selected name, an indexed name, or a slice name — A qualification (in a qualified expression), an explicit type conversion, a formal or actual designator in the form of a type conversion, or an implicit type conversion of a value of type universal_integer or universal_real to the corresponding value of another numeric type, or — A numeric literal (for a universal type), the literal null (for an access type), a string literal, a bit string literal, an aggregate, or a predefined attribute. |
| Basic signal |
A signal that determines the driving values for all other signals. A basic signal is
— Either a scalar signal or a resolved signal — Not a sub element of a resolved signal — Not an implicit signal of the form S'Stable(T), S'Quiet(T), or S'Transaction, and — Not an implicit signal GUARD. |
| Belong | (A) (to a range): A property of a value with respect to some range. The value V is said to belong to a range if the relations (lower bound <= V) and (V <= upper bound) are both true, where lower bound and upper bound are the lower and upper bounds, respectively, of the range. (B) (to a subtype): A property of a value with respect to some subtype. A value is said to belong to a subtype of a given type if it belongs to the type and satisfies the applicable constraint. |
| Binding |
The process of associating a design entity and, optionally, an architecture with an instance of
a component. A binding can be specified in an explicit or a default binding indication.
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| Bit string literal |
A literal formed by a sequence of extended digits enclosed between two quotation (")
characters and preceded by a base specifier. The type of a bit string literal is determined from the context.
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| Block |
a) The representation of a portion of the hierarchy of a design. A block is either an external block or an internal block.
b) The act of suspending the execution of a process for the purposes of guaranteeing exclusive access to either a file object or an object of a protected type. |
| Bound |
A label that is identified in the instantiation list of a configuration specification.
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| Box |
The symbol
in an index subtype definition, which stands for an undefined range. Different
objects of the type need not have the same bounds and direction.
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| Buffer |
One possible port mode. A port of mode buffer contributes its driving value to the network
containing the port; the design entity containing the port is also allowed to read its driving value.
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| Bus |
One kind of guarded signal. A bus floats to a user-specified value when all of its drivers are turned off.
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| Glossary & Definitions | |