VLSI Definitions | |
| Definitions of the terms that are often used in Chip design world. Please help us to improve the list. You can add VLSI terms and its definitions with out registering in the site. | |
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| There are 12 entries in the glossary. | |
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| Term | Definition |
| Cell | Cells are usually the simplest level at which gate array and standard cell ASIC designers design. |
| Cell library | A collection of information about ASIC cells, usually created, tested, and verified by the ASIC manufacturer for a specific fabrication process. Cell libraries given to ASIC designers include function and performance information required for circuit design on a CAD system. |
| Chip Stacking | The technique of stacking single chips to reduce the space taken by a multi-chip system. |
| circuit node | The net or interconnect between a circuit element output and all electrically connected inputs it feeds. |
| circuit port | An input or output \"pin\" of a circuit element. For example, a two-input NAND gate would have three ports--two inputs and one output. |
| CMP | Chemical Mechanical Polishing: A polishing process used to make the fabrication wafers as flat as possible. |
| Comparator | A comparator is a device that accepts two analog inputs, compares the inputs, and produces a binary output that is a function of which input is higher. |
| Conductor | Any material, such as aluminum, copper or gold, that offers little resistance to the flow of electrical current. |
| Core | A pre-designed block that requires little or no further development or verification effort to use as an element in a complex System–on-Chip (SoC) design. |
| core logic | The portion of a circuit that implements the circuit\'s primary functions. |
| CPFC - Canadian Photonics Fabrication Ce | A facility which provides prototyping, manufacturing, and testing services to universities and industry for unique photonic and optoelectronic components thereby reducing time to market. |
| CVD | A SEMICON process used to deposit material onto a wafer using chemical reactions on the wafer surface to modify the material during processing. |
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