VHDL Glossary | |
IEEE Std
1076-2002 - IEEE Standard VHDL Language Reference Manual, Copyright © 2006 by the
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| There are 18 entries in the glossary. | |
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| Term | Definition |
| Change | The signal S, of type T, is said to change value if and only if the expression “S = S’Delayed” evaluates to False, where the "=" operator in the expression is the predefined "=" on type T. |
| Character literal | A literal of the character type. Character literals are formed by enclosing one of the graphic characters (including the space and nonbreaking space characters) between two apostrophe (') characters. |
| Character type | An enumeration type with at least one of its enumeration literals as a character literal. |
| Chosen implementation | An implementation of floating-point types that conforms to either IEEE Std 754-1985 or to IEEE Std 854-1987 and with a minimum representation size of 64 bits. |
| Closely related types | Two type marks that denote the same type or two numeric types. Two array types are closely related if they have the same dimensionality, if their index types at each position are closely related, and if the array types have the same element types. Explicit type conversion is only allowed between closely related types. |
| Complete | A loop that has finished executing. Similarly, an iteration scheme of a loop is complete when the condition of a while iteration scheme is FALSE or all of the values of the discrete range of a for iteration scheme have been assigned to the iteration parameter. |
| Complete context | A declaration, a specification, or a statement; complete contexts are used in overload resolution. |
| Composite type | A type whose values have elements. There are two classes of composite types: array types and record types. |
| Concurrent statement | A statement that executes asynchronously, with no defined relative order. Concurrent statements are used for dataflow and structural descriptions. |
| Configuration | A construct that defines how component instances in a given block are bound to design entities in order to describe how design entities are put together to form a complete design. |
| Conform | Two subprogram specifications, are said to conform if, apart from certain allowed minor variations, both specifications are formed by the same sequence of lexical elements, and corresponding lexical elements are given the same meaning by the visibility rules. Conformance is defined similarly for deferred constant declarations. |
| Connected | A formal port associated with an actual port or signal. A formal port associated with the reserved word open is said to be unconnected. |
| Constant | An object whose value cannot be changed. Constants are either explicitly declared, subelements of explicitly declared constants, or interface constants. Constants declared in packages can also be deferred constants. |
| Constraint | A subset of the values of a type. The set of possible values for an object of a given type that can be subjected to a condition is called a constraint. A value is said to satisfy the constraint if it satisfies the corresponding condition. There are index constraints and range constraints. |
| Conversion function | A function used to convert values flowing through associations. For interface objects of mode in, conversion functions are allowed only on actuals. For interface objects of mode out or buffer, conversion functions are allowed only on formals. For interface objects of mode inout or linkage, conversion functions are allowed on both formals and actuals. Conversion functions have a single parameter. A conversion function associated with an actual accepts the type of the actual and returns the type of the formal. A conversion function associated with a formal accepts the type of the formal and returns the type of the actual. |
| Convertible | A property of an operand with respect to some type. An operand is convertible to some type if there exists an implicit conversion to that type. |
| Current value | The value component of the single transaction of a driver whose time component is not greater than the current simulation time. |
| Cycle pure | An expression is cycle pure if its value does not change when evaluated, repeatedly, within a given analog solution point with identical values for all its quantities. |
| Glossary & Definitions | |