VHDL Glossary | |
IEEE Std
1076-2002 - IEEE Standard VHDL Language Reference Manual, Copyright © 2006 by the
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| There are 6 entries in the glossary. | |
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| Term | Definition |
| Match | A property of a signature with respect to the parameter and subtype profile of a subprogram or enumeration literal. The signature is said to match the parameter and result type profile if certain conditions are true. |
| Matching elements | Corresponding elements of two composite type values that are used for certain logical and relational operations. |
| Member | A slice of an object, a subelement, or an object; or a slice of a subelement of an object. |
| Method | An abstract operation that operates atomically and exclusively on a single object of a protected type. |
| Mode | The direction of information flow through the port or parameter. Modes are in, out, inout, buffer, or linkage. |
| Model | The result of the elaboration of a design hierarchy. The model can be executed in order to simulate the design it represents. |
| Glossary & Definitions | |