VHDL Glossary | |
IEEE Std
1076-2002 - IEEE Standard VHDL Language Reference Manual, Copyright © 2006 by the
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| There are 4 entries in the glossary. | |
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| Term | Definition |
| Object | A named entity that has a value of a given type. An object can be a constant, signal, variable, or file. |
| Object alias | An alias whose alias designator denotes an object (that is, a constant, signal, variable, or file). |
| Out | One possible mode of a port or subprogram parameter. A port of mode out contributes a driving value to the network containing the port but cannot be read by the design entity containing the port. A subprogram parameter of mode out can be modified but not read by the containing subprogram. |
| Overloaded | Identifiers or enumeration literals that denote two different named entities. Enumeration literals, subprograms, and predefined operators may be overloaded. At any place where an overloaded enumeration literal occurs in the text of a program, the type of the enumeration literal must be determinable from the context. |
| Glossary & Definitions | |