Enter into Zilicon Zone


RocketTheme Joomla Templates


Read more...
VHDL Glossary

IEEE Std 1076-2002 - IEEE Standard VHDL Language Reference Manual, Copyright © 2006 by the IEEE. The IEEE disclaims any responsibility or liability resulting from the placement and use in this product. Information is reprinted with the permission of the IEEE. Further distribution is not permitted without consent of the IEEE Standards Department. If there is any  questions please  contact admin.


You can always search for entries.

Begins withContainsExactly matches

Submit Term/definitions/company

All | A | B | C | D | E | F | G | H | I | K | L | M | N | O | P | Q | R | S | T | U | V | W


R
There are 17 entries in the glossary.
Pages: 1
Term Definition
RangeA specified subset of values of a scalar type.
 
Range constraintA construct that specifies the range of values in a type. A range constraint is compatible with a subtype if each bound of the range belongs to the subtype or if the range constraint defines a null range. The direction of a range constraint is the same as the direction of its range.
 
ReadThe value of an object is said to be read when its value is referenced or when certain of its attributes are referenced.
 
Real literalAn abstract literal of the type universal_real that contains a base point.
 
Record typeA composite type whose values consist of named elements.
 
ReferenceAccess to a named entity. Every appearance of a designator (a name, character literal, or operator symbol) is a reference to the named entity denoted by the designator, unless the designator appears in a library clause or use clause.
 
RegisterA kind of guarded signal that retains its last driven value when all of its drivers are turned off.
 
Regular structureInstances of one or more components arranged and interconnected (via signals) in a repetitive way. Each instance may have characteristics that depend upon its position within the group of instances. Regular structures may be represented through the use of the generate statement.
 
ResolutionThe process of determining the resolved value of a resolved signal based on the values of multiple sources for that signal.
 
Resolution functionA user-defined function that computes the resolved value of a resolved signal.
 
Resolution limitThe primary unit of type TIME (by default, 1 femtosecond). Any TIME value whose absolute value is smaller than this limit is truncated to zero (0) time units.
 
Resolved signalA signal that has an associated resolution function.
 
Resolved valueThe output of the resolution function associated with the resolved signal, which is determined as a function of the collection of inputs from the multiple sources of the signal.
 
Resource libraryA library containing library units that are referenced within the design unit being analyzed.
 
Result subtypeThe subtype of the returned value of a function.
 
ResumeThe action of a wait statement upon an enclosing process when the conditions on which the wait statement is waiting are satisfied. If the enclosing process is a nonpostponed process, the process will subsequently execute during the current simulation cycle. Otherwise, the process is a postponed process, which will execute during the final simulation cycle at the current simulated time.
 
Right ofWhen a value V1 and a value V2 belong to a range and either the range is an ascending range and V2 is the predecessor of V1, or the range is a descending range and V2 is the successor of V1.
 


All | A | B | C | D | E | F | G | H | I | K | L | M | N | O | P | Q | R | S | T | U | V | W


Glossary & Definitions
VLSI-world.com