VHDL Glossary | |
IEEE Std
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| There are 27 entries in the glossary. | |
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| Term | Definition |
| Satisfy | A property of a value with respect to some constraint. The value is said to satisfy a constraint if the value is in the subset of values determined by the constraint. |
| Scalar type | A type whose values have no elements. Scalar types consist of enumeration types, integer types, physical types, and floating point types. Enumeration types and integer types are called discrete types. Integer types, floating point types, and physical types are called numeric types. All scalar types are ordered; that is, all relational operators are predefined for their values. |
| Scope | A portion of the text in which a declaration may be visible. This portion is defined by visibility and overloading rules. |
| Selected name | Syntactically, a name having a prefix and suffix separated by a dot. Certain selected names are used to denote record elements or objects denoted by an access value. The remaining selected names are referred to as expanded names. |
| Sensitivity set | The set of signals to which a wait statement is sensitive. The sensitivity set is given explicitly in an on clause, or is implied by an until clause. |
| Sequential statements | Statements that execute in sequence in the order in which they appear. Sequential statements are used for algorithmic descriptions. |
| Shared variable | A variable accessible by more than one process. Such variables must be of a protected type. |
| Short-circuit operation | An operation for which the right operand is evaluated only if the left operand has a certain value. The short-circuit operations are the predefined logical operations and, or, nand, and nor for operands of types BIT and BOOLEAN. |
| Signal | An object with a past history of values. A signal may have multiple drivers, each with a current value and projected future values. The term signal refers to objects declared by signal declarations or port declarations. |
| Signal transform | A sequential statement within a statement transform that determines which one of the alternative waveforms, if any, is to be assigned to an output signal. A signal transform can be a sequential signal assignment statement, an if statement, a case statement, or a null statement. |
| Simple name | The identifier associated with a named entity, either in its own declaration or in an alias declaration. |
| Simulation cycle | One iteration in the repetitive execution of the processes defined by process statements in a model. The first simulation cycle occurs after initialization. A simulation cycle can be a delta cycle or a time-advance cycle. |
| Single-object declaration | An object declaration whose identifier list contains a single identifier; it is called a multiple-object declaration if the identifier list contains two or more identifiers. |
| Slice | A one-dimensional array of a sequence of consecutive elements of another one-dimensional array. |
| Source | A contributor to the value of a signal. A source can be a driver or port of a block with which a signal is associated or a composite collection of sources. |
| Specification | A class of construct that associates additional information with a named entity. There are three kinds of specifications: attribute specifications, configuration specifications, and disconnection specifications. |
| Statement transform | The first sequential statement in the process equivalent to the concurrent signal assignment statement. The statement transform defines the actions of the concurrent signal assignment statement when it executes. The statement transform is followed by a wait statement, which is the final statement in the equivalent process. |
| Static name | A name in which every expression that appears as part of the name (for example, as an index expression) is a static expression (if every discrete range that appears as part of the name denotes a static range or subtype and if no prefix within the name is either an object or value of an access type or a function call). |
| Static range | A range whose bounds are static expressions. |
| Static signal name | A static name that denotes a signal. |
| Static variable name | A static name that denotes a variable. |
| String literal | A sequence of graphic characters, or possibly none, enclosed between two quotation marks (\"). The type of a string literal is determined from the context. |
| Subaggregate | An aggregate appearing as the expression in an element association within another, multidimensional array aggregate. The subaggregate is an (n–1)-dimensional array aggregate, where n is the dimensionality of the outer aggregate. Aggregates of multidimensional arrays are expressed in row-major (right-most index varies fastest) order. |
| Subelement | An element of another element. Where other subelements are excluded, the term element is used. |
| Subprogram specification | Specifies the designator of the subprogram, any formal parameters of the subprogram, and the result type for a function subprogram. |
| Subtype | A type together with a constraint. A value belongs to a subtype of a given type if it belongs to the type and satisfies the constraint; the given type is called the base type of the subtype. A type is a subtype of itself. Such a subtype is said to be unconstrained because it corresponds to a condition that imposes no restriction. |
| Suspend | A process that stops executing and waits for an event or for a time period to elapse. |
| Glossary & Definitions | |