VHDL Glossary | |
IEEE Std
1076-2002 - IEEE Standard VHDL Language Reference Manual, Copyright © 2006 by the
IEEE. The IEEE disclaims any responsibility or liability resulting from the
placement and use in this product. Information is reprinted with the permission
of the IEEE. Further distribution is not permitted without consent of the IEEE
Standards Department. If there is any questions please contact admin. | |
| You can always search for entries. | |
|
Submit Term/definitions/company | |
| Designator | (A) Syntax that forms part of an association element. A formal designator specifies which formal parameter, port, or generic (or which subelement or slice of a parameter, port, or generic) is to be associated with an actual by the given association element. An actual designator specifies which actual expression, signal, or variable is to be associated with a formal (or subelement or subelements of a formal).An actual designator may also specify that the formal in the given association element is to be left unassociated (with an actual designator of open). (B) An identifier, character literal, or operator symbol that defines an alias for some other name. (C) A simple name that denotes a predefined or user-defined attribute in an attribute name, or a user-defined attribute in an attribute specification. (D) A simple name, character literal, or operator symbol, and possibly a signature, that denotes a named entity in the entity name list of an attribute specification. (E) An identifier or operator symbol that defines the name of a subprogram. |
| Glossary & Definitions | |