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VHDL Glossary

IEEE Std 1076-2002 - IEEE Standard VHDL Language Reference Manual, Copyright © 2006 by the IEEE. The IEEE disclaims any responsibility or liability resulting from the placement and use in this product. Information is reprinted with the permission of the IEEE. Further distribution is not permitted without consent of the IEEE Standards Department. If there is any  questions please  contact admin.


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OutOne possible mode of a port or subprogram parameter. A port of mode out contributes a driving value to the network containing the port but cannot be read by the design entity containing the port. A subprogram parameter of mode out can be modified but not read by the containing subprogram.
 


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