VHDL Glossary | |
IEEE Std
1076-2002 - IEEE Standard VHDL Language Reference Manual, Copyright © 2006 by the
IEEE. The IEEE disclaims any responsibility or liability resulting from the
placement and use in this product. Information is reprinted with the permission
of the IEEE. Further distribution is not permitted without consent of the IEEE
Standards Department. If there is any questions please contact admin. | |
| You can always search for entries. | |
|
Submit Term/definitions/company | |
| Regular structure | Instances of one or more components arranged and interconnected (via signals) in a repetitive way. Each instance may have characteristics that depend upon its position within the group of instances. Regular structures may be represented through the use of the generate statement. |
| Glossary & Definitions | |