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VHDL Glossary

IEEE Std 1076-2002 - IEEE Standard VHDL Language Reference Manual, Copyright © 2006 by the IEEE. The IEEE disclaims any responsibility or liability resulting from the placement and use in this product. Information is reprinted with the permission of the IEEE. Further distribution is not permitted without consent of the IEEE Standards Department. If there is any  questions please  contact admin.


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UpdateAn action on the value of a signal, variable, or file. The value of a signal is said to be updated when the signal appears as the target (or a component of the target) of a signal assignment statement (indirectly); when it is associated with an interface object of mode out, buffer, inout, or linkage; or when one of its subelements (individually or as part of a slice) is updated. The value of a signal is also said to be updated when it is a subelement or slice of a resolved signal, and the resolved signal is updated. The value of a variable is said to be updated when the variable appears as the target (or a component of the target) of a variable assignment statement (indirectly), when it is associated with an interface object of mode out or linkage, or when one of its subelements (individually or as part of a slice) is updated. The value of a file is said to be updated when a WRITE operation is performed on the file object.
 


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