Verilog Hardware description language (or simply Verilog) is used to model hardware circuits. Verilog HDL is very powerful. It supports design, verification, and implementation of analog, digital, and mixed-signal circuits. Verilog has many variants to support above mentioned types of tasks. There is a list of all flavours of Verilog this chapter; it will give you a brief picture. This tutorial explains design / verification / implementation of digital circuits.

       Learning verilog is very easy -- Learning curve for Verilog is small

Verilog Hardware description language was invented by Phil Moorby at GDA (Gateway design Automation) in 1985. He developed first Verilog simulator called Verilog-XL. In 1989 Cadence purchased GDA. Now cadence has proprietary rights of Verilog and Verilog-XL simulator. In early 1990 Cadence released Verilog into the public domain to compete VHDL. After that popularity of Verilog dramatically increased. 

Why HDL?

Traditional circuit design methods are very lengthy and time consuming. Design produced out of traditional schematic based circuits was very difficult to debug and very complex to do verification. The advent of HDLs simplified the engineers’ effort and reduced the development time. HDL based design flow is very different from traditional design flow. It increases productivity, flexibility and reduces development cost.

Why not other programming languages?

Theoretically it is possible to model digital circuits with procedural languages like C and Java. There are some real time implementations available too. But they are lacking of two important aspects which are supported by HDLs. They are

• Concurrency. With HDLs simultaneously it is possible to execute more then one block of the code.
  
• Inclusion and handling of timing information.

Due to this it was necessary to have a new breed of programming language so called HDLs, and they are preferred to model hardware circuits over procedural languages.

Why Verilog?

Verilog was designed to be simple and powerful at multiple level of abstraction for variety of design, verification, timing, testing and synthesis tools. In general Verilog widely was used only in America and Asia. It was not so popular in Europe, now slowly Verilog is getting popular in EU as well, due to its many of rich features.