First Verilog Code

It is very usual that all programming languages are introduced with “Hello world”, program. It is easy and very helpful to do sanitary check for compiler/simulator. We follow the same tradition with our first Verilog code.

module example ( );
print (“Hello Verilog at vlsi-world.com”);
endmodule

To simulate the Verilog codes available in this tutorial, you need to install a simulator in you computer. If you are looking for a free simulator you will find many on the internet. Vlsi-world.com has an article which will guide you to download and installation a free version of ModelSim simulator, click here.

Brief introduction of Verillog structure

Verilog design consists of hierarchy or collection of design modules. These Verilog modules can communicate to each other with a set of input, output, and/or bidirectional ports. Internally, a Verilog module contains a list of wires and registers. Verilog HDL can be used to design the hardware at difference level of abstraction. Here abstraction means the level of detail of the design. The abstraction levels can be Algorithmic level, RTL level, Gate level, Switch level. Depends on the designs and needs appropriate level of abstraction is used. In general RTL level coding is widely used.
 

Verilog module structure

Every Verilog module has three different blocks, port list, declaration area, main body.

• Port list comprise list of ports with that the logic can communicate to other modules / designs.
• Declaration area defines the ports as input or output and also declares internal registers, wires and constants.
• Main body, here the functionality of the circuit defined it can be structural or algorithmic or RTL type of coding.