Description: Behavioral model of D type flip-flop. In this model asynchronous reset is used to reset the flip-flop
D Flip-Flop Model library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity DFF is
port (Reset_n : in std_logic;
Clock_In : in std_logic;
D_Input : in std_logic;
Q_Output : out std_logic);
end DFF;
architecture BEHV of DFF is
begin
D_Flip_Flop: process(Reset_n, Clock_In)
begin
if (Reset_n = '0') then
Q_Output <= '0';
elsif (Clock_In'event and Clock_In = '1') then
Q_Output <= D_Input;
end if;
end process D_Flip_Flop;
end BEHV;
Simulation output  D Flip Flop Simulation Output
Synthesis output  D Flip Flop Synthesis Output |
