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Transparent Latch VHDL model

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Description: Behavioral model of a transparent latch. It is positive level sensitive latch that is it will transfer the input to the output when the enable signal is equal to one. Otherwise it will hold the last previous value.

Transparent Latch 
 
library IEEE;
 
use IEEE.std_logic_1164.all;
 
use IEEE.std_logic_unsigned.all;
 
entity Latch is
 
    port (Latch_Open   : in std_logic;
 
          D_Input      : in std_logic;
 
          Latched_Data : out std_logic);
 
end Latch;    
 
architecture BEHV of Latch is
 
begin
 
  Latch_Data: process(Latch_Open, D_Input)
 
  begin
 
    if (Latch_Open = '1') then
 
       Latched_Data <= D_Input;
 
       -- If Latch_Open = 0, then Latch keeps its previous data
 
       -- it means the latch is closed.
 
   end if;
 
  end process Latch_Data;
 
end BEHV;

Simulation output

Transparent latch simulation output

Synthesis output

Transparent latch synthesis output

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