www.vlsi-world.com - VHDL Delay Model (Inertial and transport)

VHDL Delay Model (Inertial and transport)

Save this page

Description: The following code explains how to model transport delay and inertial delay in VHDL. Default delay in VHDL is inertial delay. For example when you use “after 5ns” VHDL consider this delay as inertial delay. When we need to have transport delay we have to use the keyword “TRANSPORT”.

Delay model - Inertial and Transport 
 
library IEEE;
 
use IEEE.std_logic_1164.all;
 
use IEEE.std_logic_unsigned.all;
 
entity delay is
 
    port (Input_A         : in std_logic;
 
          Input_B         : in std_logic;
 
          Output_inertial : out std_logic;
 
          Output_transport: out std_logic);
 
end delay;    
 
architecture BEHV of delay is
 
begin
 
   -- By default the delays are Inertial in VHDL 
 
   Output_inertial  <= NOT(Input_A AND Input_B) after 1 ns;
 
   Output_transport <= TRANSPORT NOT(Input_A AND Input_B) after 1 ns;
 
end BEHV;

Simulation output

Inertial and Transport delay model output

Enter into Zilicon Zone