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Parameterizable VHDL model (counter example)

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Description: “Generic” statement in VHDL is very useful to model parameterizable (i.e. scalable) models. It is really useful to while making library also it increases to model reuse. In the following example there is n bit counter which is used as 3 bit as well as 4 bit counter.
The n-bit counter is instantiated as a component in the top module. This component will give information about the previously defined design to the present design. This statement is very helpful to connect different modules together.

Parameterizable counter 
 
library IEEE;
 
use IEEE.std_logic_1164.all;
 
use IEEE.std_logic_unsigned.all;
 
entity n_bit_counter is
 
generic(n: INTEGER);
 
port( clk       : in std_logic;
 
      reset     : in std_logic;
 
      enable    : in std_logic;
 
      count_out : out std_logic_vector(n-1 downto 0)
 
);
 
end n_bit_counter;
 
architecture behv of n_bit_counter is      
 
    signal count_reg: std_logic_vector(n-1 downto 0);
 
begin
 
   process(clk, enable, reset)
 
   begin
 
    if reset = '1' then
 
        count_reg <= (count_reg'range => '0');
 
    elsif (clk='1' and clk'event) then
 
        if enable = '1' then
 
         count_reg <= count_reg + 1;
 
        end if;
 
    end if;
 
    end process; 
 
    -- assignment to the output port
 
    count_out <= count_reg;
 
end behv;

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