Test bench for Parameterizable counter
 
 
library IEEE;
 
use IEEE.std_logic_1164.all;
 
use IEEE.std_logic_unsigned.all;
 
entity top is
 
end top;
 
architecture BEHV of top is
 
  component n_bit_counter 
 
    generic (n : integer);  
 
    port( clk       : in std_logic;
 
          reset     : in std_logic;
 
          enable    : in std_logic;
 
          count_out : out std_logic_vector(n-1 downto 0)
 
        );
 
  end component;
 
  signal top_reset      : std_logic;
 
  signal top_enable     : std_logic;
 
  signal top_clk        : std_logic;
 
  signal top_count_out3 : std_logic_vector (2 downto 0);
 
  signal top_count_out4 : std_logic_vector (3 downto 0);
 
begin 
 
  count_3bit : n_bit_counter generic map (3) 
 
               port map (top_clk,top_reset,top_enable,top_count_out3);
 
  count_4bit : n_bit_counter generic map (4) 
 
               port map (top_clk,top_reset,top_enable,top_count_out4);
 
  CLK_GEN : process
 
  begin
 
    top_clk <= '1';
 
    wait for 1 ns;
 
    top_clk <= '0';
 
    wait for 1 ns;
 
  end process CLK_GEN;
 
  process  
 
  begin    
 
    top_reset  <= '1';
 
    top_enable <= '1'; 
 
    wait for 4 ns;
 
    top_reset  <= '0';
 
    wait for 40 ns;
 
    top_enable <= '0';
 
    wait;
 
  end process;
 
end BEHV;
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