Self checking test bench for 2-bit counter
 
 
library IEEE;
 
use IEEE.std_logic_1164.all;
 
use IEEE.std_logic_unsigned.all;
 
use std.textio.all;
 
entity tb_counter is
 
end tb_counter;
 
architecture BEHV of tb_counter is
 
  component n_bit_counter   
 
    generic (n : integer);  
 
    port(    clk       : in std_logic;
 
          reset     : in std_logic;
 
          enable    : in std_logic;
 
          count_out : out std_logic_vector(n-1 downto 0)
 
        );
 
  end component;
 
  signal top_reset      : std_logic;
 
  signal top_enable     : std_logic;
 
  signal top_clk        : std_logic;
 
  signal top_count_out2 : std_logic_vector (1 downto 0);
 
begin 
 
  count_2bit : n_bit_counter generic map (2) 
 
               port map (top_clk,top_reset,top_enable,top_count_out2);
 
  CLK_GEN : process
 
  begin
 
    top_clk <= '1';
 
    wait for 5 ns;
 
    top_clk <= '0';
 
    wait for 5 ns;
 
  end process CLK_GEN;
 
  process  
 
      variable error_count : integer := 0;
 
      variable l : line;
 
  begin    
 
    top_reset  <= '1';
 
    top_enable <= '1'; 
 
    wait for 20 ns;
 
    top_reset  <= '0';
 
    wait for 10 ns;
 
    assert (top_count_out2 = 1) report "ERROR : Test failed" severity error;
 
    if (top_count_out2 /= 1) then
 
        error_count := error_count + 1;
 
    end if;
 
    wait for 10 ns;
 
    assert (top_count_out2 = 2) report "Failed" severity error;
 
    if (top_count_out2 /= 2) then
 
        error_count := error_count + 1;
 
    end if;    
 
    wait for 10 ns;
 
    assert (top_count_out2 = 3) report "Failed" severity error;
 
    if (top_count_out2 /= 3) then
 
        error_count := error_count + 1;
 
    end if;    
 
    wait for 10 ns;
 
    assert (top_count_out2 = 0) report "Failed" severity error;
 
    if (top_count_out2 /= 0) then
 
        error_count := error_count + 1;
 
    end if;    
 
    --stop counter here
 
    top_enable <= '0';
 
    --Error Summary
 
    if (error_count = 0) then    
 
    assert (false) 
 
    report "2 bit counter verified successfully!" 
 
    severity note; 
 
  else 
 
    assert (false) 
 
    report "Failed - There may be error(s) in the design" 
 
    severity error; 
 
  end if;
 
    wait;
 
  end process;
 
end BEHV;