Advanced self checking test bench
 
 
library IEEE;
 
use IEEE.std_logic_1164.all;
 
use IEEE.std_logic_unsigned.all;
 
use std.textio.all;
 
use ieee.std_logic_textio.all;
 
entity tb_counter is
 
end tb_counter;
 
architecture BEHV of tb_counter is
 
  component n_bit_counter   
 
    generic (n : integer);  
 
    port(     clk       :   in std_logic;
 
               reset     :   in std_logic;
 
             enable    :   in std_logic;
 
           count_out :   out std_logic_vector(n-1 downto 0)
 
        );
 
  end component;
 
  signal top_reset           : std_logic;
 
  signal top_enable        : std_logic;
 
  signal top_clk                : std_logic;
 
  signal top_count_out2 : std_logic_vector (1 downto 0);
 
begin 
 
  count_2bit : n_bit_counter generic map (2) 
 
               port map (top_clk,top_reset,top_enable,top_count_out2);
 
  APPLY_STIM_FILE : process
 
      file stimulas : text open read_mode is stimuli.dat";
 
      variable l : line;
 
      variable time_value :time;
 
      variable read_as_real : real;
 
      variable valid_number, valid_value : boolean;
 
      variable valid_data : std_logic_vector(1 downto 0);
 
      variable white_space : character;
 
      variable var_reset : std_logic;
 
      variable var_enable : std_logic;
 
      variable var_clk : std_logic;
 
      variable var_expected :std_logic_vector(1 downto 0);
 
      variable error_count : integer :=0;
 
  begin    
 
     while not endfile(stimulas)loop
 
         --read a line from stim.dat file
 
         readline(stimulas,l);
 
         --read the time value from the variable "l"
 
         read(l,read_as_real,good=>valid_number);
 
         next when not valid_number;
 
         -- convert the value from stim file in to time
 
         time_value := read_as_real * 1 ns ;
 
         --wait until the time_value to be reached
 
         if (now < time_value) then
 
            wait for time_value - now;
 
         end if;
 
         --skip space from "l"         
 
         read(l,white_space);
 
         --read clock value from the "l"         
 
         read (l,var_clk,valid_number);
 
         assert valid_number REPORT "bad clock";
 
         --skip space from "l"         
 
         read(l,white_space);
 
         --read reset value from the "l"         
 
         read (l,var_reset,valid_number);
 
         assert valid_number REPORT "bad reset"; 
 
         --skip space from "l"         
 
         read(l,white_space);
 
         --read enable value from the "l"         
 
         read (l,var_enable,valid_number);
 
         assert valid_number REPORT "bad enable"; 
 
         --read expected value from the "l"
 
         read (l,var_expected);
 
         top_clk    <= var_clk;
 
         top_reset  <= var_reset;
 
         top_enable <= var_enable;
 
         wait for 1 ns;
 
         if (var_reset = '0' and var_enable = '1')then
 
            if (top_count_out2 /= var_expected)then
 
               error_count := error_count + 1;
 
               report ("I am counting");
 
           end if;
 
         end if;
 
     end loop;
 
                if (error_count = 0) then                                         
 
                   assert (false) 
 
                   report "2 bit counter verified successfully!" 
 
                   severity note; 
 
                 else 
 
                   assert (false) 
 
                   report "Failed - There may be error(s) in the design" 
 
                   severity error; 
 
                 end if;  
 
    wait;
 
  end process;
 
end BEHV;