| Mixed HDL simulation |
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Introduction
In HDL world often you will come to a point where you have to mix Verilog and VHDL. That might due to various reasons. There is talk in the industry that many companies are moving to Verilog from VHDL. But this is not a process of one or two years. It may take decades or it may not happen. So there is lot of opportunities for the designers to mix in different HDL environment. For example when there is a combined project from different teams or while using an existing IP which is different then currently using HDL (no one will recode the existing design to another HDL) then there is a necessary of mixed HDL simulation. This tutorial is an introduction to mixed HDL design/simulation with a working example. Currently most of the simulator in the market supports mixed HDL design. In this tutorial Modeslsim5.8e is used for simulation. Note: Modelsim Xilinx/Altera versions do not support mixed HDL simulation. There is another solution for this situation that is converting one HDL to another HDL by tools. There are some companies doing consultancy to convert HDL some of them provide tools to convert Verilog to VHDL and vice versa. Still it is a good idea to keep the language as it is and do the simulation when ever it is possible. In next few paragraphs the portability issues between Verilog and VHDL are discussed. This tutorial does not cover all aspects of the VHDL or Verilog. There are very few things to understand this mixed HDL simulation mechanism. Data Type mapping VHDL and Verilog have different set of data types. There may be some conflict when connecting Verilog design with VHDL and vice versa. Instantiation of one language design in another language doesn’t require any extra effort. If there is any type mismatch in the ports, results may be unexpected so it is necessary that we should be aware of this port mapping. ModelSim automatically maps the data types between languages as shown in the following sections. PART 1 Verilog parameter and VHDL Generics mapping VHDL Generics
The real value is converted to an integer by truncating the decimal portion, this happens when scalar type receives a real value. The Verilog number for time is converted to a time value according to the `timescale directive of the module.
Verilog Parameter
The type of a Verilog parameter is determined by its initial value. Verilog ports 1. The allowed VHDL types for ports connected to Verilog nets and for signals connected to Verilog ports are
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