www.vlsi-world.com - Mixed HDL simulation

Mixed HDL simulation

Save this page

Page 2 of 6

Verilog states
Verilog states are mapped to std_logic and bit as follows:

Verilog	std_logic	bit
HiZ	‘Z’	‘0’
Sm0	‘L’	‘0’
Sm1	‘H’	‘1’
SmX	‘W’	‘0’
Me0	‘L’	‘0’
Me1	‘H’	‘1’
MeX	‘W’	‘0’
We0	‘L’	‘0’
We1	‘H’	‘1’
WeX	‘W’	‘0’
La0	‘L’	‘0’
La1	‘H’	‘1’
LaX	‘w’	‘0’
Pu0	‘L’	‘0’
Pu1	‘H’	‘1’
PuX	‘W’	‘1’
St0	‘0’	‘0’
St1	‘1’	‘1’
StX	‘X’	‘0’
Su0	‘0’	‘0’
Su1	‘1’	‘1’
SuX	‘X’	‘0’

For Verilog states with ambiguous strength:
1. bit receives '0'
2. std_logic receives 'X' if either the 0 or 1 strength component is greater than or equal tostrong strength
3. std_logic receives 'W' if both the 0 and 1 strength components are less than strong

VHDL to Verilog mappings
VHDL type bit is mapped to Verilog states as follows:

bit	verilog
‘0’	St0
‘1’	St1

VHDL type std_logic is mapped to Verilog states as follows:

Std_logic	Verilog
‘U’	StX
‘X’	StX
‘0’	St0
‘1’	St1
‘Z’	HiZ
‘W’	PuX
‘L’	Pu0
‘H’	Pu1
‘-’	StX

<< Start < Prev 1 2 3 4 5 6 Next > End >>

Enter into Zilicon Zone