| Mixed HDL simulation |
|
|
Save this page
|
Page 3 of 6 2. VHDL: instantiating Verilog
Once you have generated a component declaration for a Verilog module, you can instantiate the component just like any other VHDL component. You can reference a Verilog module in the entity aspect of a component configuration; all you need to do is specify a module name instead of an entity name.
Verilog instantiation criteria A Verilog design unit may be instantiated within VHDL if it meets the following criteria: 1.The design unit is a module or configuration. UDPs are not allowed. 2. The ports are named ports 3.The ports are not connected to bidirectional pass switches (it is not possible to handle pass switches in VHDL). Component declaration A Verilog module that is compiled into a library can be referenced from a VHDL design as though the module is a VHDL entity. Likewise, a Verilog configuration can be referenced as though it were a VHDL configuration. VHDL and Verilog identifiers The VHDL identifiers for the component name, port names, and generic names are the same as the Verilog identifiers for the module name, port names, and parameter names. Any uppercase letters in Verilog identifiers are converted to lowercase in the VHDL identifier (there are some exceptions). Examples
Port clause A port clause is generated if the module has ports. A corresponding VHDL port is defined for each named Verilog port.
You can set the VHDL port type to bit, std_logic, or vl_logic. If the Verilog port has a range, then the VHDL port type is bit_vector, std_logic_vector, or vl_logic_vector. If the range does not depend on parameters, then the vector type will be constrained accordingly, otherwise it will be unconstrained.
Examples
|
|||||||||||||||||||||||||||