| Mixed HDL simulation |
|
|
Save this page
|
Page 4 of 6 3. Verilog: instantiating VHDLYou can reference a VHDL entity or configuration from Verilog as though the design unit is a module or a configuration of the same name. VHDL instantiation criteria A VHDL design unit may be instantiated within Verilog if it meets the following criteria: 1. The design unit is an entity/architecture pair or a configuration. 2. The entity ports are of type bit, bit_vector, std_ulogic, std_ulogic_vector, vl_ulogic, vl_ulogic_vector, or their subtypes. The port clause may have any mix of these types. 3. The generics are of type integer, real, time, physical, enumeration, or string. String is the only composite type allowed. SDF annotation A mixed VHDL/Verilog design can also be annotated with SDF. Appendix (simple mixed language examples) 1. VHDL instantiation in Verilog top module  Mixed HDL Simulation |