--VHDL code for 4:1 multiplexor
library ieee;
use ieee.std_logic_1164.all;
entity Mux is
port( I3:  in std_logic_vector(2 downto 0);
 I2:  in std_logic_vector(2 downto 0);
 I1:  in std_logic_vector(2 downto 0);
 I0:  in std_logic_vector(2 downto 0);
 S: in std_logic_vector(1 downto 0);
 O: out std_logic_vector(2 downto 0)
);
end Mux;
architecture behv1 of Mux is
begin
    process(I3,I2,I1,I0,S)
    begin
        -- use case statement
        case S is
     when "00" => O <= I0;
     when "01" => O <= I1;
     when "10" => O <= I2;
     when "11" => O <= I3;
     when others => O <= "ZZZ";
 end case;
    end process;
end behv1;

Verilog test bench for VHDL multiplexer

//Verilog Test Bench for 4:1 VHDL multiplexer
module mux_tb (i3,i2,i1,i0,s,o);
   input  [2:0] o;
   output [2:0] i3;
   output [2:0] i2;
   output [2:0] i1;
   output [2:0] i0;
   output [1:0]  s;
   //Drivers for output
   reg [2:0] i3;
   reg [2:0] i2;
   reg [2:0] i1;
   reg [2:0] i0;
   reg [1:0] s;
   //Error counter
   integer   error_count;
   //Generatiin test cases
   initial
     begin
 error_count = 0;
 //Assigning different values for different signals
 i3 = 3'h4;
 i2 = 3'h7;
 i1 = 3'h0;
 i0 = 3'h5;
        //Case1
 s  = 2'b00;
 #2 //wait for 2 delays
 if (o != 3'h5)
   begin
      $display("Error in case 1\n");
      error_count = error_count + 1;     
          end
        //Case2
 s  = 2'b01;
 #2 //wait for 2 delays
 if (o != 3'h0)
   begin
      $display("Error in case 2\n");
      error_count = error_count + 1;     
          end
        //Case3
 s  = 2'b10;
 #2 //wait for 2 delay
 if (o != 3'h7)
   begin
      $display("Error in case 3\n");
      error_count = error_count + 1;     
          end
        //Case4
 s  = 2'b11;
 #2 //wait for 2 delay
 if (o != 3'h4)
   begin
      $display("Error in case 4\n");
      error_count = error_count + 1;     
          end
 //Test Summary
 if(error_count)
   $display("ERROR in the design");
 else
   $display("All test cases are passed");
     end
//mux instantiation and port mapping 
   mux one(.i3(i3),.i2(i2),.i1(i1),.i0(i0),.s(s),.o(o));
endmodule