2. Verilog instantiation in VHDL top module

Mixed HDL Simulation

Verilog adder as DUT 

// Two bit adder
module adder (a,b,carry,sum);
   //Port Declarations
   input [1:0] a;
   input [1:0] b;
   output [1:0] sum;
   output  carry;
   //Drivers for output signals
   reg [1:0]  sum;
   reg   carry;  
   // combination Logic for adder
   always @ (a or b) //Sensitive to inputs a or b
     begin
         {carry,sum} = a+b; 
     end
endmodule

VHDL test bench for Verilog adder

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity ADDER_TB is      --Top level entity dosen't have any port
end ADDER_TB;
architecture TB of ADDER_TB is
    component ADDER is
    port( A: in std_logic_vector(1 downto 0);
  B: in std_logic_vector(1 downto 0); 
  carry: out std_logic;     
  sum: out std_logic_vector(1 downto 0)
    );
    end component;
    signal A, B: std_logic_vector(1 downto 0);
    signal carry: std_logic;
    signal sum:  std_logic_vector(1 downto 0);
    begin
        U_ADDER: ADDER port map (A, B, carry, sum);
    process  
 variable err_cnt: integer :=0;
    begin -- Generating test vectors
 -- case 1
 A <= "00";      
 B <= "00";
 wait for 10 ns;
 assert (sum="00") report "Sum Error!" severity error;
 assert (carry='0') report "Carry Error!" severity error;
 if (sum/="00" or carry/='0') then
     err_cnt:=err_cnt+1;
 end if;
  -- case 2  
 A <= "11";
 B <= "11";
 wait for 10 ns;  
 assert (sum="10") report "Sum Error!" severity error; 
 assert (carry='1') report "Carry Error!" severity error;
 if (sum/="10" or carry/='1') then
     err_cnt:=err_cnt+1;
 end if;
 -- case 3
 A <= "01";
 B <= "10";
 wait for 10 ns;  
 assert (sum="11") report "Sum Error!" severity error; 
 assert (carry='0') report "Carry Error!" severity error;
 if (sum/="11" or carry/='0') then
     err_cnt:=err_cnt+1;
 end if;
 -- case 4
 A <= "10";
 B <= "01";
 wait for 10 ns;   
 assert (sum="11") report "Sum Error!" severity error; 
 assert (carry='0') report "Carry Error!" severity error;
 if (sum/="11" or carry/='0') then
     err_cnt:=err_cnt+1;
 end if;
 -- case 5
 A <= "01";
 B <= "01";
 wait for 10 ns;
 assert (sum="10") report "Sum Error!" severity error;
 assert (carry='0') report "Carry Error!" severity error;
 if (sum/="10" or carry/='0') then
     err_cnt:=err_cnt+1;
 end if;
 -- summary of testbench
 if (err_cnt=0) then
     assert false
     report "Test completed successfully for adder!"
     severity note;
 else
     assert true
     report "ERROR - Expected and received results are wrong"
     severity error;
 end if;
 wait;
    end process;
end TB;

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