| Dynamic partial reconfiguration on FPGA |
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2.3 Bus MacrosBus macros are used as fixed data paths for signals going between a reconfigurable module and another module. The HDL code should ensure that any reconfigurable module signal that is used to communicate with another module does so only by first passing through a bus macro.  Placement of bus macro There are Virtex, Virtex-E, Virtex-II, and Virtex-II Pro series specific versions of the bus macro. Be sure to instantiate the version compatible to the chosen device. Each bus macro provides for 4 bits of intermodule communication. As many bus macros as needed must be instantiated to match the number of bits traversing the boundaries of the reconfigurable modules.  Boundry between modules As an example, if reconfigurable module A communicates via 32 bits to module B, then eight (32/4) bus macros will need to be instantiated to define the data paths between modules A and B. The details of bus macro usage are described in the Bus Macro Communication section.  Placement of bus macro FPGA editor Dataflow in bus macro is always unidirectional. So Bus macros configured for Data flow in only one direction and it is fixed. Xilinx Provides these Bus Macros. Also it is possible to design our won bus macros. |