| Dynamic partial reconfiguration on FPGA |
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Page 5 of 5 3.3 Verification of DPR enabled FPGA Verification is another important issue in the DPR. Since all modules of the design does not present at any particular time make the verification difficult. The following flow is adopted for verification dynamic behavior.  DPR verification flow A. References 1.Benefits of Partial Reconfiguration - Cindy Kao, Marketing Specialist, Xilinx, Inc 2.Managing Partial Dynamic Reconfiguration in Virtex-II Pro FPGAs - Philippe Butel, Gerard Habay, Alain Rachet 3.Virtex-II Pro and Virtex-II Pro X FPGA User Guide - Xilinx, Inc 4.Virtex-II Pro and Virtex-II Pro X Platform FPGAs - Complete Data Sheet – Xilinx, Inc 5.Virtex Series configuration architecture user guide - Application Note – Xilinx, Inc 9.Modular Partial Reconfiguration in Virtex FPGAs - Pete Sedcole, Brandon Blodget, James Anderson, Patrick Lysaght and Tobias Becker 7. RECONF – Design Guidelines - Martin Daněk,Manuel Moreno,Kelly Nasi,Stefano Baldacci, Gerard Habay,Alain Rachet |