"Decoder" here is so-called address decoder which decodes addresses to generate a select signal. In the following examples select signal demonstrated as a “chip select” signal.

Address Decoder

The General Description of address decoder in Verilog is as follows (it shows only the main body not the complete code). One hot encoding technique is used here.  

case (address)
   2'd0: chipSelect = 4'b0001;
   2'd1: chipSelect = 4'b0010;
   2'd2: chipSelect = 4'b0100; 
   2'd3: chipSelect = 4'b1000;
endcase

In this case the reusability becomes slightly poor. There is another description which improves the code for readability and reusability.

parameter AD_WIDTH = 2;
parameter CS_WIDTH = 4;

input [AD_WIDTH-1:0] address;
output [CS_WIDTH-1:0] chipSelect;

assign chipSelect = 1 << address;

In this case the code can be reused just by the change of the parameter values.

Address decoder is not necessary when there is a CSR (Control Status Register) implemented. Then the code changes as follows

always @(posedge ICLK or posedge IRST)begin
  if (IRST) begin
     regControl <= 0;
  end else begin
  if ((WE)&&(address==ADR_CONTROL))
     regControl <= writeData;
  end
end

How the logic will read the signal from address decoder? It is described in the following descriptions

always @(posedge ICLK or posedge IRST) begin 
  if (IRST) begin
    regControl <= 0; 
  end else begin
  if ((WE)&&(sel[4]))
    regControl <= writeData;
  end
end

It might be confusing, the description “if ((WE)&&(sel[4]))”. The bit4 of select signal is generated for this register. Other 3 bits are generated for 3 other register. This is an example of the abstraction.