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module tb_mux;
reg sel_a;
reg sel_b;
reg [3:0]data_4bit;
wire out;
initial
  begin
    data_4bit = 4'b1001;
    // input set 1
    sel_a = 1'b0;
    sel_b = 1'b0;
    // input set 2
    sel_a = 1'b0;
    sel_b = 1'b1;
    // input set 3
    sel_a = 1'b1;
    sel_b = 1'b1;
    // input set 4
    sel_a = 1'b1;
    sel_b = 1'b0;
    // input set 5
    sel_a = 1'bx;
    sel_b = 1'bx;
  end
mux dut (.sel_a(sel_a),
         .sel_b(sel_b),
         .data_4bit(data_4bit),
         .out(out));
endmodule

Since this example is just to get an idea about code coverage only statement coverage is enabled. Other coverage options can be enabled if it is needed.

Run 1

For the first run input set 1,2 and 3 are enabled 4 and 5 are disabled (disable in the sense comment the lines under the input set 4 and input set 5). For this run the code statement coverage is only 71.4%. How this is calculated?

Code Coverage run one
Code Coverage run one
In the above figure, there are two status bars for two modules. tb_mux and dut. Measuring code coverage for test bench is not important. Only the DUT has to be checked thoroughly for it is functionality that is the job of TB. So in the above picture don’t worry about tb_mux. Our interested module is DUT and it shows 71.4%. The number of executable line in the DUT is 7. Current inputs from test bench exercises only 5 statements. So 5/7 * 100 = 74.1%
Code Coverage run one Code
Code Coverage run one Code

Above figure shows the missing statements the case items 2'b10 and default. It is clear that the design is not tested completely. So the test bench has to be improved.

 
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