Safe and Glitch free clock switching
Digital circuits are often running in different clock domains. In many circumstances the clock of these circuits need to be switched while the logic (circuit) is running. The clock switching can be done in analog circuit or in digital circuit. The Implementations in this page give details of clock switching digitally. The simplest way of clock switching can be done with simple multiplexers.
Simple clock switch
Two clocks are multiplexed and selected by a signal which is generated from the internal logic. The following circuit shows the clock switching using a multiplexer. Above circuit can be described in Verilog as follows.

In the above circuit when select is ‘1’ clk_b forwarded to the output and when select is ‘0’ clk_b forwarded to the output. The switching of these clock are combination to the select signal that is selects signals immediately (on-the-fly) switches the clock with out respect of the state of the both clocks. This is not safe some time, like the following simulation of the above circuit.

The simulation output shows a Glitch on the clock path. It is due to the ‘select’ signal goes up just before the clk_b is going down. These glitches are very hazardous for any circuits. If the width of the glitch is too small they are sensed by some flip-flops and some will not. Due to this problem the output of the complete circuit is undetermined. These glitches are also leads into Metastability problems. Since glitches are very short pulses it may violate the setup and hold time of the flip-flops and output of these flip-flops are in quasi state (outputs are not determined as ‘1’ or ‘0’). Verilog realization of proceeded circuit follows.

`timescale 1ns/10ps
module clk_switch (
  // Outputs
    out_clk,   
  // Inputs  
    clk_a,
    clk_b,
    select    );  
   input clk_a;  
   input clk_b;  
   input select;  
   output out_clk; 
   reg out_clk;
   always @ (select or clk_a or clk_b)
   begin   
       if select == 1) 
          out_clk <= clk_a;   
       else      
          out_clk <= clk_b;
       end
endmodule