The logic is little complex than the simple clock switch, the clock switching will not happen immediately after switching the select signal. This circuit allows both clock settle down and switches the new clock to the circuit. It eliminates glitch or spikes in the clock signal. The safe clock switch circuit is implemented as in the following diagram.

Safe Clock switch circuit

Following figure shows the simulation of glitch free safe clock switch. For both implementations same test bench is used. Code for the test bench is available at end of the article.

Above circuit works well with related and unrelated clock. Related clocks means both clocks come from the same clock source (they are in phase) un-related clocks (they are not in the phase) are not come from the same clock source.
In this implementation the select signal registered it makes sure that the there will not be any change in the output while both clocks are high. First stage flip-flops remove the meta-stability problem. Verilog implementation for glitch free clock switch.
`timescale 1ns/100ps

module clk_switch (
   // Outputs
   out_clk,
   // Inputs
   clk_a, clk_b, select
   );

   input clk_a;
   input clk_b;
   input select;

   output out_clk;
wire   out_clk;

reg q1,q2,q3,q4;
wire or_one, or_two,or_three,or_four;

always @ (posedge clk_a)
begin
    if (clk_a == 1'b1)
    begin
       q1 <= q4;
       q3 <= or_one;
    end
end

always @ (posedge clk_b)
begin
    if (clk_b == 1'b1)
    begin
        q2 <= q3;
        q4 <= or_two;
    end
end

assign or_one   = (!q1) | (!select);
assign or_two   = (!q2) | (select);
assign or_three = (q3)  | (clk_a);
assign or_four  = (q4)  | (clk_b);

assign out_clk  = or_three & or_four;

endmodule