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It is important to develop good
syntax habits as it will save you from having to debug things later. Verilog
syntax is quite straight forward and easy to remember.
Comments
As with any programming language,
Verilog offers two ways to insert comment in your Verilog code. It is good
practice to add comments in your code.
- ' // ' The line followed by this mark will be in
ignores, useful for single line comment.
- ' /* ' ' */ ' The block or lines between these two
marks are ignored, useful for multiple lines
// This is a one line comment
/* Example of
multiple line
comment */
Case sensitivity
Verilog filenames, variables and
keywords are case sensitive unlike VHDL. 'Good', 'gooD' and 'gOOd' are treated
as different objects in Verilog.
Numbers in Verilog
Verilog has a neat syntax to
specify different kind of numbers such as decimal, binary, hexadecimal or
octal.
<size>’<base_format><value>
Size –
number of bits
Base_format ‘d’ or ‘D’ for decimal number
‘h’ or ‘H’ for
hexadecimal number
‘o’ or ‘O’ for octal
number
‘b’ or ‘B’ for binary
numbers
Value Value which you want to define
0-9
allowed for type D or d
0-9 and a-f(or A-F) allowed for type h or H
0-7 allowed for type type ‘o’ or ‘O’
1-0 allowed for type
‘b’ or ‘B’
The
character ‘_’ can be used in-between the number to increase the readability.
Following examples covers most of the possible definitions.
Examples
12’b0000_0000_1010; // 12 bit binary number
12’Hab_c; // 12 bit hexadecimal number(Note every hexadecimal number requires 4 bits.)
4’b10_22; // invalid. Only ‘0’ and ‘1’ are allowed in type ‘b’(or ‘B’)
8’b0; // 8 bit binary number value is ‘0’. It is not necessary type 8 zeros.
-4’d6; // 6 bit negative number, this defines 2’s complement of 6
8’h-ab; // invalid. ‘–‘ not permitted between number and base specification.
456; // completely valid decimal number. If there is no “base format” and “size”, by default they are decimals
3b5; // invalid. Only decimal number allowed without base format and size.
‘H1234_abcde; // valid, un-sized number are allowed for all types of numbers.
‘o3456; // octal number
/* Unsized numbers are host machine dependent. But mostly they are
stored as a 32 bit value. */
/* In Verilog ‘X’ or ‘x’ is used for unknown values, ‘z’ or ‘Z’ is used
for high impedance value. Unknown values are high impedance
values can be included in number definitions. */
12’hz; // 12 bit hexadecimal with all bits are high impedance
10'b1010_xx11_10; // 10 bit binary number, 2 bits are unknown.
Strings
The strings in Verilog are
sequences of 8-bit ASCII characters enclosed within quotation marks.
"This is an example"
As mentioned before white spaces
are not ignored inside this string. There is no special data type available to
store strings. reg should be used to store the stings. Above string example has
18 characters (including white spaces) so it nees following variable to store
the completer string
reg[8*[18-1]:0] a;
Now 'a' can hold the above string
a = "This is an example";
If you wan to include special characters like quotes(") you must use escape sequence.
text = "\"vlsi-world.com\"";
text1 =
"vlsi-world.com";
text will produce "vlsi-world.com"
text1 will produce vlsi-world.com
Use \t to insert tabs
\n to insert new lines
\\ to insert \ character
\" to insert " character
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